The present invention relates generally to data channel receivers in the field of digital communications and, more particularly, to methods and apparatus for computing sampling phase errors for sampled and equalized data channel receivers.
One of the basic problems of digital communications is to be able to extract the highest possible data rate from a given communication channel. This communication channel can have a number of different embodiments, e.g., coaxial cable, optic fiber, magnetic read/write circuit, radio link, etc.
A large class of communication channel circuits are designed to transmit discrete data at a constant rate. The data can be decoded at the receiving end by sampling the input signal at exactly the same rate (or multiple thereof) that the data was sent. No explicit timing information is sent with the data, as it would be too expensive in channel bandwidth. Thus, this timing information, or sampling clock, has to be recovered in some manner from the input signal.
FIG. 1 shows a generic communication channel receiver. The channel receiver 10 includes: a sampler 12 having an input terminal and an output terminal with the input terminal being coupled to the input terminal of the receiver 10; an equalizer 14 having an input terminal and an output terminal with the input terminal being coupled to the output terminal of the sampler 12; a decoder 16 having an input terminal and an output terminal with the input terminal being coupled to the output terminal of the equalizer 14 and the output terminal being coupled to the output terminal of the receiver 10; a timing recovery circuit 18 having input terminals and an output terminal with the input terminals being respectively coupled to the output terminals of the sampler 12, the equalizer 14, and the decoder 16; and an oscillator 20 having an input terminal and an output terminal with the input terminal being coupled to the output terminal of the timing recovery circuit 18 and the output terminal being respectively coupled to input clock terminals of the sampler 12, the equalizer 14, and the decoder 16. As is known, the oscillator 20 generates a clock signal, Clk, that is used by the other circuits within the receiver 10 that require the clock signal, i.e., the sampling circuit, the equalizing circuit, and the decoding circuit. The sampler 12 samples the input data signal, Vin, on one of the edges of the clock signal provided by the oscillator 12 and generates a sampled signal, Vs. The equalizer 14, typically a finite impulse response (FIR) filter, shapes the sampled input signal, Vs, to approximate a specific response that can be easily decoded. The decoder 16 then takes the equalized signal, Veq, and computes an estimate of the original transmitted data in the form of an output signal, Vd, using a variety of methods such as, for example, thresholding, maximum likelihood, Viterbi, etc. The timing recovery circuit 18 uses the sampled data signal (Vs), the equalized data signal (Veq), and the decoded data signal (Vd) to compute an adjustment signal, Vp, to the phase and frequency of the oscillator 20, so that the clock signal closely matches the input signal data rate.
One of the problems to be solved in the design of such a channel is to design a circuit that computes an estimate of the phase error of the sampling clock. This phase error is used to compute the phase correction that is applied to the oscillator. In the prior art, phase error is computed as follows. First, the difference between the equalized signal and the expected value of the equalized signal, Err=Veq-Vd, is computed. Second, an estimate of the slope of the equalized signal, Seq, at the sample point is computed. If the slope is positive and the error is positive, then a smaller error would have been realized by sampling earlier. Performing an analysis of the four possible cases (depending on the sign of Seq and Err), it is evident that the product Seqxc3x97Err can be used as an estimate of the phase error.
This is an effective and well tested approach, but it has some drawbacks. First, for typical equalization targets (e.g., PRML or EPRML), the slope is often times zero, and no timing information can be extracted from this particular sample. It is to be understood that the xe2x80x9ctargetxe2x80x9d of the equalization process is the type of decoding performed by the decoding circuit of the receiver and, as such, the equalization process attempts to shape the sampled waveforms in order to provide a specific response that can be easily decoded according to the type of decoding performed. Second, estimating the slope of the signal is simple for simple targets, like PRML, but very complex for complex targets, like E2PRML. For high order targets, multiple sample values have to be examined, and the slope is derived from a large table. Third, if the circuit has to target multiple equalization targets, a separate circuit has to be designed to compute the slope for each target.
The present invention provides methods and apparatus for computing an estimate of the sampling phase error for a sampled and equalized data channel receiver. Advantageously, the methodologies of the invention are applicable to all equalization targets, have simple circuit implementations, and can be designed so that the same exact circuit can be used for multiple equalization targets.
In an illustrative embodiment of the invention, a method for use in a communication channel receiver of generating a sampling phase error signal for adjustment of a sampling clock signal associated with the receiver is provided. The illustrative method includes generating a signal representative of a weighted linear combination of a predetermined number of samples of a received input signal. The combination is a function of the samples and tap-weights of a finite impulse response filter associated with the receiver. A method of computing the weighted linear combination includes choosing a representative signal of the communications channel, and then choosing weights of the weighted linear combination to compute the phase error for the representative signal using gradient descent. Next, the illustrative method includes generating an error signal representative of the difference between an equalized sequence of samples of the received input signal and a decoded sequence of samples of the received input signal. Still further, the illustrative method includes multiplying the weighted linear combination signal with the error signal to generate a phase error signal. The phase error signal is then used to generate a phase correction signal for subsequent application to the sampling clock signal. Such application serves to adjust the sampling clock signal associated with the receiver such that the sampling clock signal substantially matches a data rate associated with the input signal. Accordingly, the receiver is able to extract the highest possible data rate from the communication channel.
The present invention finds application in various fields such as, for example, the fields of wired digital networks, wireless digital networks, optical disk (CD-ROM) and magnetic disk read channels. However, it is to be appreciated that such inventive teachings may be employed in other applications not explicitly enumerated herein.